The basic architecture of most data processing systems today includes a digital processor and random access memory. For economic reasons, the random access memory ("RAM") is often dynamic random access memory ("DRAM").
Typical operating frequencies for asynchronous DRAMs are in the range of 33 Mhz. For system clock rates above this range, the DRAM becomes a bottleneck that forces the processor and other components to wait for memory access. The same problem exists for more expensive memories as well, such as static random access memory ("SRAM"), electrically erasable programmable read-only memory ("EEPROM"), other programmable read-only memory ("PROM"), and read-only memory ("ROM").
Recently, synchronous dynamic random access memories ("SDRAM") have been proposed to take better advantage of inherent DRAM bandwidth. With synchronous DRAMs, data is clocked in and out of the memory device at relatively high rates. Due to certain standardization agreements, synchronous DRAMs have only a few operating modes. These operating modes are typically controlled by an operation mode register. Such a register may be, for example, a 7-bit wide register. Although such a register allows for 128 operating modes, synchronous DRAMs operate in only a few modes, a number which is much less than 128. Thus, misprogramming of the operation mode register with an invalid operating mode can occur, resulting in indeterminate device operation.
Indeed, this problem exists in any integrated circuit where user programmable registers are employed to allow changing between operating modes, and where, for an n-bit register, less than 2.sup.n operating modes are available.
The indeterminate device operation that results from entry of invalid operating modes is highly undesirable.